M.Tech (VLSI Design)

Program Code 13819

Campus Gurgaon (Manesar)

Institute Amity School of Engineering and Technology, Gurgaon (Manesar)

University Amity University Haryana

Eligibility B.Tech.-CSE/ECE/IT

Duration 2 Years

Selection Process

  • Program Fee (Rs. in Lacs)
  • 1st Year Non Sponsored Semester 0.74

Course Structure

1st Year

Semester 1

  • FRENCH-I
  • GERMAN-I
  • SPANISH-I
  • RUSSIAN-I
  • CHINESE-I
  • PORTUGUESE-I
  • KOREAN-I
  • JAPANESE-I
  • HINDI-I
  • SEMICONDUCTOR DEVICE PHYSICS & MODELING LAB
  • VLSI PROCESSING & TECHNOLOGY
  • SEMICONDUCTOR DEVICE PHYSICS & MODELING
  • ANALOG CMOS DESIGN
  • SYNTHESIS & OPTIMIZATION OF DIGITAL CIRCUITS
  • DIGITAL VLSI DESIGN
  • CIRCUIT & DEVICE LAB
  • ANALOG CMOS DESIGN LAB
  • ADVANCED SIMULATION LAB
  • BASICS OF COMMUNICATION
  • SELF DEVELOPMENT AND INTERPERSONAL SKILLS

Semester 2

  • FRENCH-II
  • GERMAN-II
  • SPANISH-II
  • RUSSIAN-II
  • CHINESE-II
  • PORTUGUESE-II
  • KOREAN-II
  • JAPANESE-II
  • DIGITAL SYSTEM DESIGN USING SYSTEM VERILOG
  • LOW POWER VLSI DESIGN
  • ASIC DESIGN
  • SYSTEM VERILOG PROGRAMMING LAB
  • LOW POWER VLSI DESIGN LAB
  • MINOR LAB PROJECT-I
  • BEHAVIOURAL COMMUNICATION & RELATIONSHIP MANAGEMENT
  • CORPORATE COMMUNICATION
  • PROCESSOR ARCHITECTURE FOR VLSI
  • ADVANCED DIGITAL DESIGN USING VHDL
  • MEMS & IC INTEGRATION
  • OPTICAL SEMICONDUCTOR TECHNOLOGY & DEVICES
  • ADVANCED INSTRUMENTATION & SYSTEM DESIGN
  • RF & MIXED SIGNAL
  • ADVANCED DIGITAL SIGNAL PROCESSING

2nd Year

Semester 3

  • FRENCH-III
  • GERMAN-III
  • SPANISH-III
  • RUSSIAN-III
  • CHINESE-III
  • PORTUGUESE-III
  • KOREAN-III
  • JAPANESE-III
  • SOC DESIGN
  • ALGORITHMS FOR VLSI
  • VLSI TESTING
  • SOC DESIGN LAB
  • ALGORITHMS FOR VLSI LAB
  • SUMMER INTERNSHIP EVALUATION
  • LEADING THROUGH TEAMS
  • INTERPERSONAL COMMUNICATION
  • NANO SCIENCE AND TECHNOLOGY
  • ARTIFICIAL INTELLIGENCE & FUZZY SYSTEM
  • ADVANCED DIGITAL IMAGE PROCESSING
  • WIRELESS COMMUNICATION
  • ADVANCED EMBEDDED SYSTEM
  • WIRELESS SENSOR NETWORK
  • RELIABILITY ENGINEERING

Semester 4

  • DISSERTATION-RESEARCH PROJECT